April 6th, 2020 – By Ed Sperling

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources.

To see the video on the SemiEngineering page, please click HERE. 

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See other SemiEngineering tech talk videos here.