Arteris Articles

Arteris IP is Hiring a UI Developer!

Featured Position!

UI Developer in Campbell, CA

We are looking for an experienced User Interface (UI) Developer to participate in the development of our next generation network-on-chip (NoC) interconnect design and optimization software.

 Apply Now!

Topics: software jobs artificial intelligence arteris ip noc interconnect job SoC designs C++ Java modeling simulation

Arteris IP is Hiring in Campbell, CA! Senior Software Engineering Manager

Featured Position!

Senior Software Engineering Manager in Campbell, CA

We are looking for an experienced Senior Software Engineering Manager who will report to the VP of Engineering. 

You, as a successful candidate, are dynamic and self-motivated with excellent organizational, and technical skills who can effectively communicate across all levels of management. The ideal candidate will be an experienced leader who is visionary, strategic, technology savvy and skilled in contemporary software technologies and architectures. You will own and drive both development and quality engineering across multiple development teams.

Candidates must have the ability to influence thinking or gain acceptance of others in potentially sensitive situations. A thorough understanding of product development and excellent people management skills is also critical.

Topics: software jobs artificial intelligence arteris ip noc interconnect job SoC designs C++ Java

Semiconductor Engineering: Edge Complexity To Grow For 5G

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Edge Complexity To Grow For 5G

July 2nd, 2019 - By Kevin Fogarty and Ed Sperling

Increased interdependence of technologies will drive different architectures and applications. 

It gets even more complicated in the automotive world than other any other markets because of safety-critical circuitry.

“You may have to reboot part of the chip for a failed operation, while keeping the rest of it operating in a safe state,” said Kurt Shuler, vice president of marketing at Arteris IP. “If you think about the space shuttle or a Boeing 777, the black boxes are 20 pounds. You can’t have that in a car. There is a lot of functional safety being done at the microprocessor level to save cost. That can be used to spy on what’s happening at the system level, so if there are problems you can isolate them and in a safe state and fail gracefully. If there is a transient error, you reboot.”

For more information, please download the Arteris FlexNoC AI Package data sheet; http://www.arteris.com/download-flexnoc-ai-package-datasheet

Topics: SoC functional safety FPGAs semiconductor engineering flexnoc ai package noc interconnect ML

EE Times article, SoC Interconnect: Don't DIY!

Kurt Shuler, VP Marketing at Arteris IP, explains why a DIY approach to building your own configurable interconnect IP product is not as easy as one may think.

June 13, 2019 - by Kurt Shuler

The recent market consolidation might have some companies considering whether this is a do-it-yourself (DIY) project that your company should consider taking on. Whether it’s a simple crossbar switch or a full-function network-on-chip (NoC) architecture for advanced SoCs, all that’s needed are the right people with the right knowledge and a big budget; eventually, it could happen. But the question isn’t can you do it? It’s should you do it?

Topics: semiconductor eetimes autonomous vehicles AI automotive design SoCs kurt shuler noc interconnect ML/AI