Semiconductor Engineering: Power Optimization: What’s Next?

by Madelyn Miller, On May 18, 2021

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What’s Next!

May 17th, 2021 – By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.


“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

To read the entire SemiEngineering article, please click here:

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