Arteris Articles

Semiconductor Engineering: Verification Signoff Beyond Coverage

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Verification Signoff Beyond Coverage

February 3rd, 2022 - By Paul Graykowski

semiengineering-logo-2020Ensuring implementation and verification match the customer's requirements.


A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. This process iterates until the agreed level of coverage is met. Functional coverage is the metric by which this process is gauged, and it works well within its scope. The major electronic design automation (EDA) vendors have tools to run simulations, accumulate coverage statistics, and help further advance those metrics. But this is not the whole story in signoff.

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To read the entire article on SemiEngineering, please click here:https://semiengineering.com/verification-signoff-beyond-coverage/?cmid=c66ef7cb-b8e4-4424-afdd-ab3326bab94f

Topics: network-on-chip automotive semiconductor engineering arteris ip verification SoCs compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski