Home » Newsroom » Blog » Semiconductor Engineering: Von Neumann Is Struggling

Semiconductor Engineering: Von Neumann Is Struggling

Jan 18, 2021
Brian Bailey
< 1 min read

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

To read the entire SemiEngineering article, please click here: https://semiengineering.com/von-neumann-is-struggling/

Blogs

Latest Blogs

Blog

EDN: Last-level cache has become a critical SoC design element

As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully

Learn more about this

Blog

SemiWiki: Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain

As RISC-V adoption grows across commercial and government programs, integrating third-party IP cores introduces supply chain security challenges that require structured, design-level assurance. This article highlights a scalable, CWE-based methodology demonstrated by Cycuity (an Arteris brand) with SiFive and BAE

Learn more about this

Blog

Semiconductor Engineering: AI Energy Gap and Chiplets: Why Data Movement Matters

At the panel discussion at Chiplet Summit 2026, where Arteris was among the experts, participants emphasized that efficient AI chiplets require more than fast physical links like UCIe—they demand smart, system-level architecture around data movement, coherency, and protocol choice. As

Learn more about this

Blog

Electronic Design: Bridging the Gap to Chiplet Interoperability

This article examines the gap between today’s tightly managed multi-die implementations and the long-term vision of true multi-vendor chiplet interoperability. It explains how companies are deploying homogeneous and heterogeneous architectures, why proprietary flows still limit plug-and-play integration, and how standards

Learn more about this

Blog

EE Times: The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation

As semiconductor architectures scale toward chiplets, multi-die SoCs, and AI-driven workloads, data movement—not raw compute—has emerged as the primary limiter of performance, power, and scalability. The article argues that network-on-chip fabrics are becoming the true center of gravity in modern

Learn more about this

Blog

Semiconductor Engineering: Solving Real-World AI Bottlenecks

This article explains how modern AI SoCs are increasingly limited by data movement and memory latency rather than raw compute. It highlights the role of efficient interconnects and shared last-level caches in reducing latency, power consumption, and DRAM traffic, and

Learn more about this