Next generation ASIL B(D) autonomous driving systems to be enabled by ISO 26262-compliant cache coherent and non-coherent interconnect IP
CAMPBELL, Calif. — July 10, 2018 — Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced that Mobileye has purchased multiple licenses of Arteris IP Ncore Cache Coherent Interconnect, FlexNoC Interconnect, and the Ncore and FlexNoC Resilience Packages for functional safety and artificial intelligence (AI) hardware acceleration. This broad portfolio of Arteris IP interconnect technology will be the on-chip communications backbone of Mobileye’s next-generation ISO 26262 ASIL B(D) capable next generation EyeQ system-on-chip (SoC) devices.
We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC Resilience Packages for functional safety, we trust Arteris IP to be the highest performing and safest choice for ISO 26262-compliant NoC IP.”
Elchanan Rushinek, Vice President of Engineering, Mobileye
The Mobileye team is one of Arteris IP’s oldest and most innovative customers, having first licensed Arteris FlexNoC interconnect IP in 2010 while continually using it as the on-chip interconnect for the EyeQ3, EyeQ4, and EyeQ5 SoC families.
Mobileye chose the Ncore Cache Coherent interconnect and accompanying Resilience Package because it enables the ability to create multiple on-chip cache coherent subsystems encompassing their proprietary heterogeneous programmable hardware accelerators. These subsystems work together to accelerate the execution speed, increase the computational bandwidth, and reduce the power consumption of machine learning and AI algorithms that execute at near-real time latencies as a car is driving. The unique Ncore capability that allows this is the highly configurable Ncore Proxy Cache, which permits multiple hardware accelerators to be organized into clusters that participate as full coherent peers in a cache coherent system. The highly configurable Ncore Cache Coherent interconnect saves to Mobileye the time and effort that would be required to create clusters of these processing elements with their own custom level 2 caches, and also optimizes the use of system bandwidth by eliminating communications to a centralized cache directory.
“We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators,” said Elchanan Rushinek, Vice President of Engineering, Mobileye. “And with our prior experience using FlexNoC and the FlexNoC Resilience Packages for functional safety, we trust Arteris IP to be the highest performing and safest choice for ISO 26262-compliant NoC IP.”
“The sophistication of city driving ADAS SoCs is staggering, to the point that cars in the next few years will become supercomputers on wheels. Such chips require the most advanced, flexible and resilient interconnect to execute multiple simultaneous neural network and machine learning use cases while ensuring data protection for ISO 26262 functional safety compliance,” said K. Charles Janac, President and CEO of Arteris IP. “We have partnered with Mobileye for multiple generations of SoCs, and we are honored to have our interconnect IP portfolio, encompassing our Ncore, FlexNoC, PIANO, and Resilience products, be a strategic part of Mobileye’s latest SoC project.”
About Arteris IP
Arteris IP provides network-on-chip (NoC) interconnect IP to accelerate system-on-chip (SoC) semiconductor assembly for a wide range of applications from AI to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye, and Texas Instruments. Arteris IP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, the CodaCache standalone last level cache, and optional Resilience Package (ISO 26262 functional safety) and PIANO automated timing closure capabilities. Customer results obtained by using the Arteris IP product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit www.arteris.com or find us on LinkedIn at https://www.linkedin.com/company/arteris.
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