Silicon Valley, Austin and Paris, France facilities build-out accommodates growth in engineering capabilities
CAMPBELL, Calif. — October 31, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the expansion of its worldwide office infrastructure to accommodate its accelerated growth in engineering talent and design momentum in the artificial intelligence and automotive markets.
ArterisIP’s investments in our engineering team and facilities are a testament to our commitment to SoC interconnect IP technology leadership.
K. Charles Janac, President and CEO, ArterisIP
Over the last 3 years, ArterisIP has grown more than 100 percent to nearly 90 employees, with engineers accounting for two-thirds of the team. Driven by this growth, the company has greatly increased its worldwide facilities footprint in the following locations:
- Silicon Valley, California, USA – Construction of the new ArterisIP headquarters, allows the company to consolidate nearly 50 employees currently working in two separate buildings and provides room for additional employees;
- Austin, Texas, USA – ArterisIP recently completed the build-out of a new engineering site in Austin with room for 15 employees;
- Paris, France – The company just doubled the size of its Paris office to meet the needs of new engineering hires working on interconnect IP development.
Expanding engineering capabilities in Silicon Valley, Austin and Paris boosts ArterisIP’s presence in engineering epicenters to tap expertise for on-chip interconnect, networking, software tools, embedded software, verification and functional safety. In addition, close proximity to the company’s semiconductor and systems customers allows ArterisIP to be more responsive to input and feedback.
“Meeting the on-chip interconnect technology challenges of new markets like autonomous driving and machine learning requires a holistic engineering approach to address customer needs with expertise from multiple disciplines including hardware and software development and verification, system-level architectural prowess, and world-class quality and safety,” said Joe Butler, Vice President of Engineering at ArterisIP.
“Our growth in engineering employees and engineering sites has been driven by the needs of our semiconductor and systems customers, who require a high level of hardware IP, software and system-level innovation in order to create the new generation of SoCs for innovative applications like machine learning and autonomous driving,” said K. Charles Janac, President and CEO of ArterisIP. “ArterisIP’s investments in our engineering team and facilities are a testament to our commitment to SoC interconnect IP technology leadership.”
ArterisIP provides system-on-chip (SoC) interconnect IP to accelerate SoC semiconductor assembly for a wide range of applications from automobiles to mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye (Intel), Altera (Intel), and Texas Instruments. ArterisIP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, as well as optional Resilience Package (ISO 26262 functional safety) and PIANO automated timing closure capabilities. Customer results obtained by using the ArterisIP product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit www.arteris.com or find us on LinkedIn at www.linkedin.com/company/arteris.
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Arteris, ArterisIP, FlexNoC, Ncore, PIANO, and the ArterisIP logo are trademarks of Arteris, Inc. All other product or service names are the property of their respective owners.